基于FPGA的超高速跳频接收机设计与实现

Design and Implementation of Ultra-High Speed Hopping Receiver Based on FPGA

在当今信息化、智能化时代,跳频通信设备面临的电磁环境极为复杂,提高跳速可增强其抗干扰性。基于此,研究基于现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的超高速跳频通信系统。相比于其他频率合成器,直接式数字频率合成器(Direct Digital Synthesizer,DDS)的切换速度较快,波形实际跳速超过70000跳/秒,非常适合于实现超高速跳频功能。DDS以RS码作为编译码方式,可以增强系统容错性,采用MSK调制解调方式使得波形包络恒定且易于传输,从实验仿真和FPGA工程资源消耗分析,其满足波形设计要求,可达到良好的跳频通信性能。

In the era of information and intelligence,the electromagnetic environment faced by frequency hopping communication equipment is extremely complex,and increasing the hopping speed can enhance its anti-interference performance.Based on this,this paper studies the ultra high speed frequency hopping communication system based on FPGA.Compared with other frequency synthesizers,Direct Digital Frequency Synthesizer(DDS)has faster switching speed and is very suitable for implementing ultra high speed frequency hopping.The actual hopping speed of this waveform exceeds 70000 hops per second.The RS code is used as its encoding and decoding method to enhance the fault tolerance of the system,and the MSK modulation and demodulation method makes the waveform envelope constant and easy to transmit.From the experimental simulation and FPGA project resource consumption analysis,both meet the waveform design requirements and can achieve good frequency hopping communication performance.