一种RGMII接口电平不匹配的研究与实现

Research and Implementation of RGMII Interface Level Mismatch

针对目前的国际形式和各方面对核心芯片的国产化需求,Hi3559AV100作为一款强大SoC芯片,具有卓越的图像处理能力,在各种视频传输和智能处理方面应用越来越广泛。然而国产PHY芯片的I/O电平推荐为2.5 V,无法直接和海思的RGMII接口对接,本文利用FPGA的BANK供电灵活性设计了Hi3559AV100+FPGA+GC88E1111的千兆以太网的设计方案,设计简单通用、灵活便利,能够满足高速数据传输的性能需求,为千兆以太网PHY芯片和其他MAC对接时接口电平不匹配问题提供了一种新的解决方案。

In response to the current international situation and the localization needs of core chips from all parties,Hi3559AV100 has excellent image processing capabilities and is more and more widely used in various video transmission and intelligent processing.However,the recommended I/O level of the domestic PHY chip is 2.5 V,which cannot be directly connected to the HiSilicon RGMII interface.The article uses FPGA BANK power supply flexible design of the Gigabit Ethernet design scheme of Hi3559AV100+FPGA+GC88E1111,the design is simple,universal,flexible and convenient,which can meet the performance requirements of high-speed data transmission,and the interface level does not match when the Gigabit Ethernet PHY chip is docked with other MACs.The problem provides a new solution.