一种动态调节前沿消隐电路

A Dynamic Regulation Leading Edge Blanking Circuit

基于原边反馈反激变换器结构,提出了一种适用于PWM、PFM调节模式的动态调节前沿消隐电路。首先,当系统工作在PWM或PFM模式时,分别检测输出电流信息和系统工作频率,产生动态调节的前沿消隐信号,避免了辅助绕组高频振荡导致的膝点电压误采样。其次,通过动态调节前沿消隐时间,减小了全负载范围内膝点采样电路的功耗。设计的原边峰值电流采样电路能获得输出电流信息和系统工作频率信息,避免了反激变换器工作条件变化时前沿消隐时间非线性调节导致的膝点电压误采样。基于0.18μm BCD工艺对电路进行设计。仿真结果表明,该电路产生的动态调节前沿消隐时间误差的最小值为4%。

Based on topological structure of primary side feedback flyback converter, a dynamic regulation leading edge blanking circuit suitable for PWM、PFM regulation mode was proposed. First, when the system was working in PWM or PFM mode, the output current information and the system operating frequency were detected respectively to generate the dynamically regulated front blanking signal, which avoiding the miss-sampling of knee voltage caused by high frequency oscillation of the auxiliary winding. Secondly, the front blanking time was dynamically adjusted to reduce the power consumption of the lap sampling circuit in the full load range. The designed sampling circuit could obtain the output current information and the working frequency information of the system, which avoiding the miss-sampling of the knee voltage caused by the nonlinear adjustment of the blanking time when working conditions of the flyback converter were changed. The circuit was designed in a 0.18 μm BCD process. The simulation results showed that the minimum error of dynamic regulation leading edge blanking time was 4%.