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A super-junction SOI-LDMOS with low resistance electron channel 被引量:1

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摘要 A novel super-junction LDMOS with low resistance channel(LRC),named LRC-LDMOS based on the silicon-on-insulator(SOI)technology is proposed.The LRC is highly doped on the surface of the drift region,which can significantly reduce the specific on resistance(R^(on,sp))in forward conduction.The charge compensation between the LRC,N-pillar,and P-pillar of the super-junction are adjusted to satisfy the charge balance,which can completely deplete the whole drift,thus the breakdown voltage(BV)is enhanced in reverse blocking.The three-dimensional(3D)simulation results show that the BV and R^(on,sp)of the device can reach 253 V and 15.5 mΩ·cm^(2),respectively,and the Baliga's figure of merit(FOM=BV^(2)/R^(on,sp))of 4.1 MW/cm^(2)is achieved,breaking through the silicon limit.
作者 陈伟中 黄元熙 黄垚 黄义 韩郑生 Wei-Zhong Chen;Yuan-Xi Huang;Yao Huang;Yi Huang;Zheng-Sheng Han(College of Electronics Engineering,Chongqing University of Posts and Telecommunications,Chongqing 400065,China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China)
出处 《Chinese Physics B》 SCIE EI CAS CSCD 2021年第5期607-612,共6页 中国物理B(英文版)
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