基于AXI-DMA总线控制器的HDMI视频多帧缓存架构处理系统设计

Design of HDMI Video Multi-frame Buffer Architecture Processing System Based on AXI-DMA Bus Controller

随着高清音视频产业的快速发展,视频信号处理系统对图像的编解码处理和传输提出了低时延、高带宽的要求。目前越来越多的高速实时图像采集系统,不仅信号的采集速率越来越高,而且图像数据量也越来越大,因此设计一种高速大容量的图像数据缓存及传输系统具有十分重要的意义。针对这一问题,本文提出了一种视频多帧缓存架构处理系统,利用FPGA作为视频信号系统处理平台的核心,通过读取标准视频流FHD(1920*1080@60Hz)图像信号进行解码,并经过AXI-DMA总线进入DDR3内存设备中并缓存三帧,然后通过AXI-DMA总线将DDR3中缓存数据读出到FPGA的内存控制器的FIFO中,最后通过数据编码实现HDMI格式输出和显示。本处理系统依托于FPGA的AXI-DMA总线控制器与DDR设备高速信号的传输和处理的效率,具有低时延和高带宽的信号处理特点,广泛应用于工业显示和实时监控等专业显示领域。

With the rapid development of high-definition audio and video industry,video signal processing systems requires low-latency and high-bandwidth for image encoding and decoding processing and transmission.At present,there are more and more high-speed real-time image acquisition systems with increasing higher signal acquisition rate and larger image data volume.Therefore,it is very important to design an image data buffering and transmission system with high speed and large capacity.Aiming at the problem,this article puts forward a video multi-frame buffer architecture processing system which uses FPGA as the core of the video signal system processing platform to decode FHD(1920*1080@60Hz)image signal by reading standard video stream,and enters DDR3 memory device through AXI-DMA bus.Three frames are buffered in parallel,and the buffered data in DDR3 is read into the FIFO of the FPGA memory controller.Finally,the HDMI format output and display are realized through data encoding.The processing system relies on the high-speed signal transmission and processing efficiency of the FPGA's AXI-DMA bus controller and DDR equipment,with the features of low-latency and high-bandwidth for signal processing.It is widely used in professional display fields such as industrial display and real-time monitoring.