一种20 MS/s基于VCO比较器的二阶噪声整形SAR ADC设计

A 20 MS/s second-order noise shaping SAR ADC with VCO-based comparator

基于压控振荡器(VCO)结构的比较器,提出了一种二阶噪声整形逐次逼近型(NS-SAR)模数转换器(ADC)。首先采用对电源电压敏感度较低且噪声性能更优越的VCO比较器,随后通过动态放大器优化噪声传递函数的零极点,最后通过噪声整形结构抑制信号带内噪声。基于180 nm CMOS工艺,设计了一款12位20 MS/s NS-SAR ADC。仿真结果表明,在1.3 V电源电压下,功耗为1.12 mW,过采样率(OSR)为8时,信号噪声失真比(SNDR)为72.7 dB,无杂散动态范围(SFDR)为88 dB,优值(FoMs)为163 dB;并且在1.3~1.8 V电源电压范围内,其有效位数(ENOB)>11.7 bit。

A second-order noise-shaping successive approximation register(NS-SAR)analog-to-digital converter(ADC)with a voltage-controlled oscillator(VCO)-based comparator is presented in this paper.Firstly,a VCO-based comparator with low voltage sensitivity and better noise performance is adopted.Then the zero pole of the noise transfer function is optimized by the dynamic amplifier.Finally,the noise in the signal band is suppressed by the noise shaping structure.A design example of 12 bit 20 MS/s NS-SAR ADC was fabricated in a 180 nm CMOS technology.Simulation results show that,it consumes 1.12 mW at a 1.3 V power supply and achieves a FoMs of 163 dB with 72.7 dB SNDR,88 dB SFDR at an oversampling ratio(OSR)of 8,and the effective number of bits(ENOB)>11.7 bit in the supply voltage range of 1.3~1.8 V.