先心病心音CNN分类算法的硬件加速

CNN model hardware acceleration for classifier of CHD heart sound

为提高先心病心音分类算法的实时性,适用于资源有限的嵌入式设备,提出一种对FPGA进行流水线约束设计的硬件加速方法。将CNN内部计算的并行性与FPGA上的并行硬件对应起来,通过VIVADO高层次综合(HLS)映射CNN算法至FPGA上,在卷积层中的循环上采用流水线约束,子循环会默认展开的方式,提升循环的执行速度。实例仿真计算结果表明,该方法可以很好地利用硬件资源,极大降低计算延时,有效提升算法的实时性。

To improve the real-time nature of the heart sound classification algorithm for congenital heart disease,a method of pipeline constraint design for FPGA was proposed.It was suitable for embedded devices with limited resources.This method combined the parallelism of CNN internal calculation with parallel hardware on FPGA,and mapped CNN algorithm to FPGA through VIVADO high-level synthesis.Pipeline constraints were used on the loop in the convolution layer,and the sub-loop would be expanded by default,which improved the execution speed of the loop.Results of the simulation indicate that the proposed method can make good use of hardware resources,greatly reduce the calculation delay,and effectively improve the real-time performance of the algorithm.