基于非等径双球堆积模型和蒙特卡罗仿真模拟的纳米铜烧结互连机理分析

Study on the mechanism of nano-copper particles sintering interconnection based on a non-isodiametric double sphere stacking model and Monte Carlo simulation

为了满足第三代半导体低温封装、高温服役的要求,纳米金属颗粒烧结封装互连逐渐替代传统钎料回流焊工艺,而高致密度烧结是实现高可靠性封装的必要条件之一.为了研究纳米铜颗粒烧结互连机理,首先通过非等径双球三维密集堆积模型构建理论颗粒配比与堆积孔隙率之间的关系,然后采用蒙特卡罗仿真模拟不同粒径比的双球模型颗粒烧结过程,最后通过纳米铜混合烧结试验来验证理论推算和仿真模拟结果.结果表明,根据3种三维密集堆积模型估算,孔隙率最低时的颗粒粒径比在10∶1~5∶1之间;仿真模拟结果显示,粒径比为5∶1时的双球模型收缩率最大;选择250和50 nm两种粒径纳米铜进行混合烧结试验,证实烧结致密度最佳条件时的颗粒质量比为8∶1,与理论计算结果相符.由此可见,该方法可以为纳米铜烧结在第三代半导体封装互连中的应用和工艺优化提供了理论支持.

To meet the requirements of low temperature packaging and high temperature operation for wide bandgap semiconductors,the traditional reflow soldering is gradually substituted by the metallic nanoparticle sintering interconnection.However,the high sintering densification is one of necessities to achieve the high reliable packaging.To reveal the mechanism of nano-copper particles sintering interconnection,this paper firstly establishes the relationship between the particle size ratio and the stacking porosity through the three-dimensional(3D)non-isodiametric double sphere stacking modeling.Then,the Monte Carlo simulation is performed to investigate the sintering process of nano-copper particles with different size ratios.Finally,a sintering experiment with the mixture of two types of nano-copper particles is used to validate the proposed models and simulations.The results show that,according to three 3D stacking models,the stacking porosity is lowest when the particle size ratio is between 10∶1 and 5∶1.Through the Monte Carlo simulation,the model with a particle size ratio of 5∶1 has the largest sintering shrinkage.The experiment by mixing the 250 nm and 50 nm nano-copper particle shows the highest relative density of sintered samples when the particle mass ratio is 8∶1,which is consistent with the theoretical calculations.Thus,the proposed method in this study can provide theoretical supports to the nano-copper sintering interconnection application and process optimization in the wide bandgap semiconductor packaging.