LDPC自适应最小和译码算法及其FPGA实现

LDPC Adaptive Minimum Sum Decoding Algorithm and Its FPGA Implementation

低密度奇偶校验码(Low-density Parity-check,LDPC)置信传播算法性能优异且被证明接近香农极限,但需要极其复杂的对数和三角函数运算,不利于现实使用。尽管最小和算法提高了计算的方便性和适用性,但也削弱了其译码能力。为了减少误码率(Bit Error Rate,BER)的损失,利用输入变量节点边信息绝对值的最小值、次小值和双曲正切函数的关系,引入自适应乘性因子提升算法性能。仿真结果显示,自适应最小和算法的性能比传统的对数似然比置信传播算法(Log-Likelihood Ratio Belief Propagation,LLR BP)提升了0.2 dB。此外,通过在Xilinx公司的FPGA平台上进行硬件测试,实现了155码长的LDPC码最小和算法仿真。

The belief propagation(BP)decoding algorithm for low-density parity-check(LDPC)codes has been shown to approach the Shannon limit,however it requires extremely complex logarithmic and trigonometric functions,which is not of practical interest.The minimum sum(MS)algorithm improves the convenience speed and simplifies the calculation at the expense of loss in decoding performance.In order to reduce the loss in bit error rate(BER),this paper introduce an adaptive multiplicative factor which considers the relationship between the absolute value of the input variable node side information,the second smallest value and the hyperbolic tangent function.As a result,the performance of the proposed adaptive MS algorithm is 0.2 dB superior to the traditional LLR(Log-Likelihood Ratio)BP algorithm.Also,LDPC codes of 155 lengths are implemented based on the Xilinx FPGA platform.