基于CORDIC的低功耗复合计算架构

CORDIC⁃based low⁃power composite computing architecture

在大数据量计算的雷达成像系统研究中,降低匹配函数的资源占用与功耗是重要的研究课题,而除法与平方根是匹配函数中计算的核心.提出一种在坐标旋转数字计算机(Coordinate Rotation Digital Computer,CORDIC)中利用附加函数计算平方根和除法的无乘法器且可靠的设计架构,消除了在不同硬件上计算平方根与除法的限制.在保证计算速度与精度的前提下,低资源占用与低功耗是该架构的显著特征.在Xilinx Virtex⁃6(XC6vlx240t)上完成16 bit精度电路的硬件仿真实验,该结构的最大时钟频率为201 MHz,实例电路在UMC 90 nm技术节点下以1 MHz的频率在ASIC上实现.与以往的类似工作相比,该结构减少了84.23%的Slice LUTs,节省77.02%的功耗,并在最大时钟频率上有所提升.同时,对提出的架构进行了误差分析,16 bit精度电路在平方根与除法计算中的平均绝对误差(Mean Absolute Error,MAE)分别为1.8×10^(-4)和2.7×10^(-4).为进一步可视化误差,还进行了比特位误差(Bit Position Error)实验.

In the research of radar imaging system with large amounts of data computing,reducing the resource occupation and power consumption of matching functions is an important research topic.Division and square root are the core of the calculation in the matching functions.In this paper,a multiplier⁃free and reliable design architecture to compute square root and division using computation of additional functions in coordinate rotation digital computer(CORDIC)is proposed.The designed architecture eliminates the requirement of a separate hardware for square root and division computation.On the premise of ensuring the computing speed and accuracy,low resource occupation and low power consumption are the significant features of the architecture.Hardware experiment with 16 bit circuits was done on Xilinx Virtex⁃6(XC6vlx240t).The max clock frequency of the proposed architecture is 201 MHz.The example circuits are implemented under UMC 90 nm technology node with 1 MHz on ASIC.Compared with the state of the art,it reduced 84.23%Slice LUTs and saved 77.02%power consumption.Besides,the max clock frequency increased.At the same time,this paper analyzes the error of the proposed architecture.The mean absolute error(MAE)of 16 bit precision circuits for square root and division are 1.8×10^(-4) and 2.7×10^(-4) respectively.In order to further visualize the error,the bit position error experiment was performed.