摘要
随着电子设备信号传输速率的提高,电路板布线密度增大,PCB设计对信号完整性的影响越来越大。为了解决电子产品设计初期信号完整性问题,以DDR4高速并行总线为例,改变DDR4数据传输线PCB设计参数,采用无码间干扰方法仿真测试,得到合理的PCB布线方法,提高信号的完整性。同时对网络负载端阻抗不匹配问题进行RC并联阻抗匹配优化,有效地解决高速信号完整性问题。
With the increase of signal transmission rate of electronic equipments and the increase of wiring density of circuit board,the influence of PCB design on signal integrity is becoming greater and greater.In order to solve the signal integrity problem in the initial stage of electronic product design,taking DDR4 high-speed parallel bus as an example,change the PCB design parameters of DDR4 data transmission line,and adopt non inter-code interference method to carry out the simulation test,so as to obtain a reasonable PCB wiring method and improve the signal integrity.At the same time,in view of the problem of impedance mismatch of the network load,the RC parallel impedance matching optimization is carried out to solve effectively the problem of high-speed signal integrity.
作者
李芳
LI Fang(Software Engineering Institute of Guangzhou,Guangzhou 510990,China)
出处
《现代信息科技》
2021年第4期43-47,共5页
Modern Information Technology
基金
2020年广东高校教师特色创新研究项目(2020DZXX07)。
