基于超低电压的片上分组交换路由器设计

Design of a Low Voltage On-Chip Package Switching Router

片上网络(NOC)因其具有的高并行度、低延时和良好的可扩展性等特点,而被广泛用于多核/众核处理器的核间互联通信。降低工作电压是降低处理器功耗、提升电路能效的有效手段。本文面向超低电压的多核/众核处理器,提出了基于EDAC (Error Detection and Correction)技术和三相时钟流水线的片上分组交换路由器结构,并基于该结构设计了4×4的2D Mesh NOC。采用TSMC28HPC工艺,完成了芯片设计。后仿结果表明,在0.4V下,该路由器最高工作频率达到61.73MHz,比Baseline电路相比提高了7.4%,每个路由器一个周期的平均能耗仅为2.07 pJ。

Network On Chip( NOC) is widely used in inter-core communication of multi-core processors because of its high parallelism,low latency and good scalability. Reducing the working voltage is an effective way to reduce the processor power consumption and improve the circuit energy efficiency. For ultra-low voltage multi-core processors,the paper proposes an on-chip packet switching router architecture based on EDAC( Error Detection And Correction) technology and three-phase clock pipeline,and designs a 4 × 4 2D mesh NOC based on the architecture. The chip is implemented by TSMC28HPC process. The simulation results show that the maximum operating frequency of the router is 61. 73 MHz at 0. 4 V,which is 7. 4% higher than that of baseline circuit. And the average energy consumption of each router in one cycle is only 2. 07 pJ.