自主FPGA芯片软件时序参数提取方法

Method to Extract the Timing Parameters for Self-Design FPGA

静态时序分析是FPGA应用开发中非常重要的功能,它能验证用户设计在时序上的正确性。静态时序分析软件所需输入的时序参数直接影响分析结果的正确性。介绍了一种仿真结合实测的方法,能比较准确地提取时序参数。实验结果表明,基于自主FPGA芯片的软件时序参数,通过静态时序软件分析,能够比较准确地反映FPGA芯片时序,可满足国产软件时序参数自主替代的需求。

Static timing analysis is a vital functionality in FPGA development and application,which verifies the timing constraints on user's design.The parameters those STA software needs influence the validity of result directly.A method that combines simulation and actual measurement to extract timing accurate parameters is introduced.The experiment results show that the software timing parameters based on the independent FPGA chip can accurately reflect the timing of chip through the STA analysis and meet the domestic software timing parameters replacement requirements.