基于SystemC参考模型的UVM验证平台设计

Design of UVM Verification Platform Based on SystemC Reference Model

随着集成电路设计复杂度的不断提高,作为芯片开发周期中重要一环的芯片验证已经出现了逐渐乏力的趋势,传统的验证主要使用直接测试的方法,验证工程师们需要编写大量定向测试用例来满足验证的需求,这个过程既费时又费力,因此需要寻找新的验证方法来加快验证速度,提高验证效率。基于SystemC语言具有的强大的高层次建模能力以及UVM验证方法学具有的激励随机化、复用性高、以覆盖率为导向等诸多优势,结合SystemC语言和UVM验证方法学来搭建验证平台。使用基于SystemVerilog语言的UVM验证方法学搭建验证环境,并将SystemC语言编写的模型作为参考模型接进UVM验证平台,对超高频射频识别数字基带处理单元中读写器发送链路进行验证,统计覆盖率。结果表明,代码覆盖率和功能覆盖率均达到100%,满足了芯片验证要求,相比于传统验证方法有效地缩短了验证时间,提高了验证效率。

With the increasing complexity of integrated circuit(IC)design,chip verification,as an important part of chip development cycle,has become increasingly weak.Traditional verification mainly uses direct testing methods.Verification engineers need to write a large number of directional test cases to meet the requirements of verification.This process is time-consuming and laborious,so it is necessary to find new verification methods to speed up verification and improve verification efficiency.Based on the powerful high-level modeling capability of SystemC language and the advantages of UVM verification methodology such as incentive randomization,high reusability and coverage orientation,a verification platform is built by combining SystemC language and UVM.The UVM based on SystemVerilog language is used to build the verification environment,and the model coding by SystemC language is connected into the UVM verification platform as the reference model to verify the UHF RFID physical layer forward link baseband circuit.The results show that the code coverage and function coverage reach 100%,which meet the chip verification requirements.Compared to traditional verification methods,it greatly shortens the verification time and improves the verification efficiency.