期刊文献+

一种高精度片内电阻校准电路设计 被引量:2

Design of a High-Precision Calibration Circuit for On-chip Resistances
下载PDF
导出
摘要 设计了一种适用于40Ω~100Ω内调节的高精度片内电阻校准电路,该电路可精确调整因工艺波动产生变化的片内电阻阻值。片内电阻校准电路采用模数混合控制方法,即以片外电阻为基准,采用高精度回滞比较器比较片内和片外电阻转换的电压值,采用自适应控制电路精确调整电阻阵列开关,使得片内电阻的阻值与片外基准电阻的阻值相等。电路基于40nm CMOS工艺进行设计,仿真结果表明,比较器的电压比较阈值最小为2mV,电路实现40Ω~100Ω内电阻阻值可调节,校准误差小于2%。 A high precision on-chip resistance calibration circuit with the adjustment range of 40Ωto 100Ωwas designed,which could accurately calibrate the on-chip resistance value caused by process fluctuation.The analogdigital mixing method was used.Combined with adaptive control circuits and high precision hysteresis comparators,the voltage values converted by the on-chip resistance and the referenced off-chip resistance were compared.The circuit was designed to make the on-chip resistance value equal to that of the referenced off-chip.The calibration circuit was designed in a 40nm CMOS process.The simulation results showed that the minimum voltage comparison threshold of comparator was 2mV.The circuit could achieve adjustable resistance values in the range of 40Ωto 100Ω,and the calibration error was less than 2%.
作者 韦雪明 熊晓惠 侯伶俐 WEI Xueming;XIONG Xiaohui;HOU Lingli(Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing,Guilin,Guangxi 541004,P.R.China;Chengdu Sino Microelectronics Technology Co.,Ltd,Chengdu 610041,P.R.China)
出处 《微电子学》 CAS 北大核心 2021年第3期336-340,346,共6页 Microelectronics
基金 广西无线宽带通信与信号处理重点实验室主任基金项目资助(GXKL06190110) 广西高校中青年教师基础能力提升项目(2018KY0197) 广西桂林电子科技大学研究生科研创新项目(2019YCXS017)。
关键词 高精度比较器 片内电阻校准 自适应控制方法 high precision comparator on-chip resistance calibration adaptive control method
  • 相关文献

参考文献4

二级参考文献38

  • 1高彬,孟桥,郝俊.工作时钟1GHz超高速电压比较器设计[J].电子器件,2007,30(2):454-456. 被引量:1
  • 2李建中,魏同立.一种CMOS动态闩锁电压比较器的优化设计[J].电路与系统学报,2005,10(2):48-52. 被引量:6
  • 3程剑平,魏同立.低踢回噪声锁存比较器的分析与设计[J].微电子学,2005,35(4):428-432. 被引量:7
  • 4Me1 Bazes.Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers[J].IEEE Journal of Solid-State Circuits,1991,26(2):165-168.
  • 5Sumanen L,Wai Tari M,Halonen K A I.A 10-Bit 200 MS/s CMOS Parallel Pipeline A/D Converter[J].IEEE Journal of Solid-State Circuits,2001,36(7):1048-1055.
  • 6Behzad Razavi.Principles of Data Conversion System Design[M].IEEE Press,1997.
  • 7Behzad Razavi,B Wooley.Design Techniques for High-Peed,High-Resolution Comparators[J].IEEE J Sol Sta Circ,1992,27(12):1916-1926.
  • 8Jacob Baker R,Harry W Li,David E Boyce.CMOS Circuit Design,Layout,and Simulation[M].Beijing:China Machine Press.2006.
  • 9Jozef C Mitros,Chin-yu Tsai,Hisashi Shichijo,et al.High-Voltage Drain Extended MOS Transistors for 0.18-μm Logic CMOS Process[J].IEEE Transactions on Electron Devices,2001,48(8):1751-1755.
  • 10YASUDA T R,YAMAMOTO M,NISHI T.A power-on reset pulse generator for low voltage application[C]//IEEE Int Symp Circ and Syst.Sydney,NSW,Australia.2001,4:599-601.

共引文献11

同被引文献15

引证文献2

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部