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基于响应曲面建模的LS频段VCO优化设计 被引量:2

Optimization Design of a LS-Band VCO Based on Response Surface Modeling
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摘要 提出了一种采用响应曲面(RSM)协同优化压控振荡器(VCO)的功耗、相位噪声的方法。以差分耦合LC-VCO电路为实验设计对象,在电路结构上增加级联交叉耦合负阻管结合外部电流镜偏置,改进了相位噪声和功耗性能。在此基础上,建立VCO性能的响应曲面模型,优化并选取最佳电路设计参数的组合,获取最佳性能。基于TSMC CMOS 65nm、1.8VRF工艺的实验结果表明,优化后的VCO各项性能指标均显著提升。该VCO的调谐范围达2.377GHz~2.583 GHz,即206MHz,相位噪声为-113.44dBc/Hz@1MHz,功耗低至0.66mW,FoM值达184.27 dBc/Hz。该LS频段VCO适用于WiFi、物联网等无线通信中射频收发集成电路。 A response surface methodology(RSM)based optimization method for improving the performance of a LS-band voltage controlled oscillator(VCO)was proposed.A LC-VCO circuit was designed as an optimization target,and the phase noise and power dissipation were improved by employing cascade cross-coupled transistors as load-resistance and an external current mirror bias.Furthermore,the RS model was constructed by fitted data based on circuit simulations,then the best design parameters and the corresponding electric performance could be obtained as the optimal solution.Based on TSMC CMOS 65nm/1.8 V RF process,the final results showed that all performances of the proposed VCO were improved significantly after optimization.The VCO had a tuning range of 2.377GHz~2.583GHz,i.e.206MHz,aphase noise of-113.44dBc/Hz@1MHZ,and a power consumption lower than 0.66mW.The FoM value could reach 184.27dBc/Hz.The proposed LS-band VCO could be applied to the RF transceiver integrated circuits in WiFi,Internet of Things(IoT)and other wireless communications.
作者 段文娟 刘博 张金灿 孟庆端 DUAN Wenjuan;LIU Bo;ZHANG Jincan;MENG Qingduan(School of Electrical Engineering,Henan University of Science and Technology,Luoyang,Henan 471023,P.R.China)
出处 《微电子学》 CAS 北大核心 2021年第3期368-373,共6页 Microelectronics
基金 国家自然科学基金资助项目(61704049,61804046) 河南省科技厅重点科技攻关项目(192102210087,182102210295)。
关键词 压控振荡器 响应曲面建模 优化设计 相位噪声 VCO RSM optimization design phase noise
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  • 1王勇,姚宏颖,王子宇.基于锁相环的10.709 Gbit/s时钟数据再生模块[J].电子学报,2005,33(8):1509-1511. 被引量:1
  • 2Zhang Xiaowei,Hu Qingsheng.A 6.25Gbps CMOS 10B/8B decoder with pipelined architecture[J].Journal of semiconductors,2011,32(4):045009-1-4.
  • 3Jayesh Patil,Lili He,Morris Jones.Clock and data recovery for a 6 Gbps SerDes receiver[A].Conference on Computer Science and Information Technology[C].Chengdu:IEEE,2010.217-221.
  • 4Sally Safwat,Ezz El-Din Hussein,Maged Ghoneima,et al.A 12Gbps all digital low power SerDes transceiver for on-chip networking circuits and systems[A].International Symposium on Circuits and Systems[C].Rio de Janeiro:IEEE,2011.1419-1422.
  • 5Mike Harwood,Steffen Nielsen,Andre Szczepanek,et al.A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications[A].2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers[C].San Francisco:IEEE,2012.326-327.
  • 6Jri Lee,Behzad Razavi.A 40-Gb/s clock and data recovery circuit in 0.18μm CMOS technology[J].IEEE Journal of Solid-State Circuits,2003,38(12):2181-2190.
  • 7Young-Ho Kwak,Yongtae Kim,Sewook Hwang,et al.A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65nm CMOS process[J].IEEE Transactions on Circuits and Systems Ⅰ:Regular Papers,2013,60(2):303-313.
  • 8Arash Zargaran-Yazd,Shahriar Mirabbasi.12.5-Gb/s full-rate CDR with wideband quadrature phase shifting in data path[J].IEEE Transactions on Circuits and Systems Ⅱ:Express Briefs,2013,60(6):297-301.
  • 9Ansgar Pottb(a)cker,Ulrich Langmann,Hans-Ulrich Schreiber.A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s[J].IEEE Journal of Solid-State Circuits,1992,27 (12):1747-1751.
  • 10Zhou Mingzhu,Sun Lingling,Wang Guangyi,et al.Designing 3.125GHz bang-bang PLL for clock recovery in 6.25 Gbps backplane communication receiver[A].2010 International Conference on Microwave and Millimeter Wave Technology[C].Chengdu:IEEE,2010.639-942.

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