低成本的∑△ADC数字抽取滤波器设计

Design of low cost∑△ADC digital decimation filter

设计了一种低成本的64倍降采样数字抽取滤波器,对∑△ADC的输出码流进行滤波和抽取.为节省面积和保证稳定性,首先选用2抽取级联的滤波器实现方式;其次对单级滤波器进行结构优化,采用更省面积的折叠转置结构;在此基础上对系数相乘与加法部分进行了系数优化和公共项提取;最后采用Modelsim进行了电路仿真,验证了功能.通过优化,可降低寄存器和加法器的使用至优化前的59%和35%,资源优化率达到了41%和65%.数字抽取滤波器采用SMIC 0.18μm CMOS工艺实现,工作电压3.3 V,芯片面积为1.13 mm*0.36mm,功耗为5.3 mW.芯片功能测试结果表明:∑△ADC数字抽取滤波器工作正常,是一种兼顾面积和功耗的设计电路.

A low-cost 64 times down sampling digital decimation filter is designed to filter and extract the output stream of∑△ADC.In order to save the area and ensure stability,a two-decimation cascaded filter type is selected firstly.Secondly,the structure of the single-stage filter is optimized,and the folded transposition structure with less area is adopted;on this basis,the coefficient optimization and common term extraction of the coefficient multiplication and addition part are carried out.Finally,the circuit simulation and function verification are carried out with Modelsim.Through optimization,the cost of registers and adders can be reduced to 59%and 35%versus before optimization,which means the resource optimization rate can reach 41%and 65%.The digital decimation filter is implemented in SMIC 0.18μm CMOS process.The operating voltage is 3.3 V,the chip area is 1.13 mm*0.36 mm,and the power consumption is 5.3 mw.The results of chip function test show that the sigma delta ADC digital decimation filter works normally,and it is a design circuit that takes into account the area and power consumption.