基于FPGA的并行数字滤波器设计和实现

Design and Implementation of Parallel Digital Filter Based on FPGA

该文介绍了基于FPGA的并行数字滤波器设计方案,主要叙述了建立M×N维滤波矩阵、并行滤波运算以及滤波结果的处理等并行数字滤波过程。首先基于并行的路数M和滤波器的阶数N建立M×N维滤波矩阵X_(M×N),滤波矩阵X_(M×N)的每行与固定的滤波器系数矩阵H1×N进行相乘相加运算得到滤波的中间结果Y_(k+j+1(n)),然后经过截取有效量化位数最终得到并行滤波结果Y(n)。基于该并行数字滤波方案,设计了八路并行成形滤波器。经过实验验证,该八路并行成形滤波器实现了625Msps,QPSK调制格式的基带信号成形滤波,滤波的数据结果经过解调分析的EVM达到了0.326%。该文提出的并行数字滤波器设计方案通用性强,可以广泛应用于高速数字信号处理中。

This paper introduces the design of parallel digital filter based on FPGA and mainly describes the process of parallel digital filtering,such as the establishment of M×N multidimensional filtering matrix,parallel filtering operation and the processing of filtering results.Firstly,a M×N multidimensional filtering matrix X_(M×N) is established based on the number of parallelpaths M and the order N of the filter,each row of the filter matrix X_(M×N) is multiplied and added with the fix filter coefficient matrix H1×N to obtain the intermediate result of the filter Y_(k+j+1(n)),then the parallel filtering result Y(n)is obtained by intercepting the effective quantization bits.Based on this parallel filtering design,eight parallel shaping filters are designed.The experimental results show that the 8-way parallel shaping filter achieves 625 Msps,QPSK modulation format baseband signal shaping filter,and the EVM of filtering data result after demodulation analysis reaches 0.326%.The design of parallel digital filter proposed in this paper is universal and can be widely used in high-speed digital signal processing.