改进数字锁相细分方法的FPGA电路设计

Design of Modified Digital Phase-locking Subdivision Circuit Based on FPGA

为实现动态测量中光栅莫尔信号的细分,针对传统的数字锁相细分方法存在锁定时间长、频率分辨率低、易受输入信号波动影响等缺点,提出一种改进数字锁相细分方法,在详细分析改进数字锁相细分方法的原理基础上,基于现场可编程门阵列(FPGA)开展改进锁相细分方法的电路设计,重点对小数分频方法中各个模块的实现过程进行介绍,并开展实验验证电路功能。实验证明,在不同的动态工况下,电路均能够实现改进数字锁相细分方法预定的128倍细分功能,通过与传统数字锁相细分方法对比,改进数字锁相细分方法具有信号快速锁定、分辨率高、动态响应快的优点。

In this paper,a modified digital phase-locking subdivision method for realizing the subdivision of grating moirésignal in dynamic measurement was proposed,which overcomed the disadvantages of long locking time,low frequency resolution and high sensitivity to fluctuations in the input signal caused by traditional digital phase-locking subdivision method.Based on the detailed analysis of the principle of the improved digital phase-locked subdivision method,the circuit design of the improved phase-locked subdivision method was carried out based on field programmable gate array(FPGA).The realization process of each module in the fractional frequency division method was introduced emphatically,and the circuit function was verified by experiments.Experimental results show that the circuit can achieve the 128-fold subdivision function predetermined by the improved digital phase-locked subdivision method under different dynamic conditions.Compared with the traditional digital phase-locking subdivision method,the modified digital phase-locking subdivision method has the advantages of fast locking,high resolution and good dynamic characteristics.