一种适用于改进P/E循环性能NAND闪存设计方法

A reliable method for improving NAND Flash P/E cycling performance

随着NAND闪存工艺尺寸的缩小,为了确保闪存阈值电压分布在相对狭窄的区间,通常使用ISPP/ISPE(步进式编写操作/步进式擦除操作)对闪存操作。但是随着P/E循环的增加,相应的操作时间也随之改变,会极大的影响闪存的性能。因此本设计对传统ISPP/ISPE进行改良,通过使用额外的寄存器,针对P/E循环次数的不同阶段,调整ISPP/ISPE操作参数,使系统在不同的P/E循环次数下,仍能维持稳定的擦写性能。

In the recent years,the NAND Flash process scale is shrinking down smaller and smaller,to ensure the distribution of threshold voltage is narrow,normally adopt ISPP/ISPE(incremental step pulse programming/incremental step pulse erasing).But with the number of P/E cycling increasing,the performance would continually change.In this design,conventional ISPP/ISPE scheme would be optimized;a new set of register would be used to adjust operation bias according to P/E cycling numbers.So with different P/E cycling numbers,the performance would keep stable.