一种连续型Sigma-Delta ADC

A Continuous Time Sigma-Delta ADC

在无线通信系统中,低功耗宽带模数转换器一直是近几年的研究热点之一。连续型Sigma-Delta ADC采用模拟调制器和过采样噪声整形技术实现宽带高精度模数转换,在速度、集成度和成本方面更有优势。论文采用三阶三位量化反馈架构实现了一种800MHz采样速率,25MHz信号带宽的连续型Sigma-Delta ADC,此外,采用了动态元件匹配(DEM)技术克服多位量化产生的DAC失调问题并增加了零点技术进一步提高信噪比,同时设计了单边反馈的放大器架构以降低系统功耗。基于55nm工艺,在电源电压1.2V下,仿真结果表明此ADC的信噪比达到70dB,调制器环路功耗25mW,芯片总功耗70mW。

Wideband and low power ADC has been one of the research focuses in wireless communication.The CT Sigma-Delta ADC uses analog modulator and oversampled noise shaping technology to achieve broadband and high-precision,which has advantages in terms of speed,integration and cost.An 800 MS/s,25MHz output data rate CT Sigma-Delta ADC is implemented in this paper by using the third order 3-bit cascade resonators feedback form(CRFB).In addition,the dynamic element matching(DEM)technology is adopted to overcome the mismatch of DAC caused by multi-bit quantization and the zero-point technology is added to further improve the SNR.At the same time,the single-side common feedback OPA is designed to reduce the power consumption of the system.Based on 55nm,the simulation results shows that the ADC achieves 70dB SNR.The power consumption of the modulator is 25 mWand in total the ADC dissipates 68 mWfrom 1.2-V supply.