TSN交换机调度器设计与实现

Design and Implementation of Scheduler Used in TSN Switch

针对时间敏感网络(Time-Sensitive Networking,TSN)交换机设计需求,提出了一种交换电路设计方案,包括以太网帧处理电路、转发查找电路、交换单元、队列管理器和调度器。调度器可支持严格优先级调度算法、门控调度算法(即时间感知整形器)和基于信用的调度算法,并研究了算法实现机制和完整的处理流程。整个设计在基于Xilinx Virtex-6的FPGA开发平台上进行了仿真分析,给出了关键电路仿真波形,验证了调度器可支持时间敏感业务流的确定性传输。

To meet the design requirements of time-sensitive network switch, a design scheme of switch circuit is presented, which includes Ethernet frame processing circuit, forwarding lookup circuit, switching unit, queue manager and scheduler. The scheduler can support strict priority scheduling algorithms, gating scheduling algorithm and credit-based algorithm and its implementation mechanism and complete processing flow of the algorithm are introduced. The whole design is simulated and analyzed on the Xilinx Virtex-6 FPGA development platform, and the simulated waveform of the key circuit indicates that the scheduler can support the deterministic transmission of time-sensitive stream.