基于FPGA硬件的单粒子翻转模拟技术

FPGA Based Single Event Upset Simulation Technology

由于航空航天活动越发复杂,深空通信和姿态控制等航空航天电子系统大量采用集成电路芯片以提高各方面性能。随着集成电路工艺节点的进一步缩小,电路受到单粒子效应而发生错误的概率越来越大。评估集成电路对单粒子翻转(Single event upset,SEU)的敏感性对航空航天的发展具有重要意义。电路规模的增加和系统功能集成度的提高给评估速度带来了严峻挑战。本文提出了一种能适用于超大规模集成电路(Very large scale integration,VLSI)的快速故障注入方法。该方法可通过脚本自动分析电路,并修改逻辑使电路具备故障注入功能。实验结果表明,该方法实现的故障注入速度可以达到纳秒级,可大幅缓解电路规模和评估时间之间的矛盾,从而满足VLSI的评估需求。

Due to the increasing complexity of aerospace exploration,integrated circuits are applied in many aerospace electronic systems such as deep space communication and attitude control.With the further shrinking of integrated circuit technology,the probability of errors in circuit due to single event effects has become higher.Evaluating the sensitivity of integrated circuits to single event upset(SEU)is of great significance to the development of aerospace.The continuous increase of circuit scale and the improvement of system function integration pose severe challenges to the speed of evaluation.For this reason,this paper proposes a fast fault injection method suitable for very large scale integration(VLSI).This method can automatically analyze the circuit through scripts,and modify the logic to make the circuit available for fault injection.Experiment results show that the fault injection speed can reach nanosecond level,which can alleviate the contradiction between circuit scale and evaluation time.Consequently,it can meet the evaluation requirements of VLSI.