基于FPGA的模板匹配加速器的设计与实现

Design and implementation of template matching accelerator based on FPGA

本文针对当前基于计算机视觉的织物瑕疵检测系统在实时性及经济性上无法满足实际生产需求这一问题,对瑕疵检测领域的模板匹配算法进行了改进、设计并实现了一种基于FPGA的模板匹配算法加速器。为了提升加速器的工作效率,深入分析了该加速器架构的处理时延,并从访存时延、传输时延、计算时延3个方面对加速器进行了优化,提升了总线带宽的利用率。实验结果表明,该加速器使得传统的模板匹配算法在时钟频率为150 HMz的Zynq-7000平台上获得了33 MHz的像素处理速率,即每秒可处理分辨率约为8192×4096大小的织物图片,与通用CPU i7-8750H相比,性能是其10.5倍,满足了实时性需求。同时该解决方案采用SoC技术取代了传统的PC级板卡式结构,降低了系统成本,应用前景广阔。

In order to solve the problem that the current fabric defect detection system based on computer vision fail to meet the demands of manufacturing process in terms of real-time and economic performance,the template matching algorithm in defect detection field was improved,and a template matching algorithm accelerator based on FPGA was designed and implemented.In order to improve the working efficiency of the accelerator,the processing delay of the accelerator architecture is deeply analyzed,and the accelerator is optimized from three aspects:access delay,transmission delay and computation delay,which improves the utilization of the bus bandwidth.Experimental result shows that the accelerator enables traditional template matching algorithms to achieve a pixel processing rate of 33 MHz on the Zynq-7000 platform with a clock rate of 150 MHz,that is,the accelerator can process a fabric image with the resolution of 8192×4096 per second.Compared with i7-8750H,the performance is 10.5 times higher than that of i7-8750H,which meets the real-time performance requirements.At the same time,the solution uses SoC technology to replace the traditional PC board structure,which reduces the cost of the system and has a broad application prospect.