基于Verilog HDL的异步FIFO设计

Design of asynchronous FIFO based on Verilog HDL

针对解决SOC内部跨时钟域之间数据传输、存储所引起的亚稳态问题,采用异步FIFO,它是解决集成电路亚稳态的有效方法之一。文中分析了异步FIFO设计中的2个关键性技术难点:减少亚稳态出现概率和正确产生空/满状态标志位。采用一种新的设计方案,即利用格雷码计数器和二级同步器可以有效解决亚稳态问题,通过格雷码指针产生空/满状态位,以上问题迎刃而解。通过Modelsim仿真测试,结果表明,该异步FIFO数据写入和读出正常且空/满标志信号正确。

Asynchronous FIFO is one of the effective methods to solve the metastable problem caused by the data transmission and memory between clock domains in SOC.Two key technical difficulties are analyzed in asynchronous FIFO design:reduces the probability of metastable state and the generation of empty/full state markers.A new design scheme using gray counter and secondary synchronizer can effectively solve the metastable state problem,and the gray pointer can be used to determine the empty/full state bit.Through Modelsim simulation test,the results show that the asynchronous FIFO data writing and reading are normal and the empty/full signal is correct.