基于Kintex⁃7 FPGA的DDR3 SDRAM高速访存控制器优化与实现

Optimization and implementation of DDR3 SDRAM high⁃speed access memory controller based on Kintex⁃7 FPGA

针对高速视频图像在跨时钟域数据交互中存在的帧交错及DDR3 SDRAM带宽利用率较低的问题,提出一种新的DDR3 SDRAM访存控制方法,实现多路视频数据快速、高效访存。以Kintex⁃7 FPGA为控制核心,在VIVADO MIG IP核基础上,实现读写位宽比为10∶1的异步FIFO,并结合RAM构建读写缓存控制模块,提高DDR3 SDRAM带宽利用率。设计不完全乒乓操作,并采用分区缓存确保帧数据完整。对8路分辨率为1920×1080的RGB888视频图像数据进行并行读、写操作。实验结果表明,该系统能有效实现8路高速视频数据的访存,帧完整,系统的有效带宽利用率可达74.69%,图像帧率可达48 Hz。满足了高分辨率实时图像显示要求,克服了帧交错问题,提高了DDR3 SDRAM的有效带宽利用率,具有较强的可移植性,为进一步实现多路视频数据协同处理提供了参考。

In order to solve the problems of interleaved frame and low DDR3 SDRAM bandwidth utilization existing in the cross⁃domain high⁃speed video data interaction,a new DDR3 SDRAM(synchronous dynamic random access memory)control method is proposed to achieve the rapid and efficient access to multi⁃channel video data.The Kintex⁃7 FPGA is taken as the control core of the system.On the basis of VIVADO MIG IP core,an asynchronous FIFO with the read⁃to⁃write bit width ratio of 10:1 is implemented.The read⁃write cache control module is constructed by combining the FIFO with RAM to improve the DDR3 SDRAM bandwidth utilization.The incomplete ping⁃pong operation and partition cache are designed to ensure the integrality of frame data.The parallel read and write operations for 8⁃channel RGB888 video image data with a resolution of 1920×1080 are performed.The experimental results indicate that the system can effectively realize 8⁃channel high⁃speed video data access memory and provide complete frame;the effective bandwidth utilization can reach 74.96%and the frame rate can reach 48 Hz.The system can meet the real⁃time display requirements of multi⁃channel high⁃resolution images,has overcome the problem of frame interleaving and has improved the effective bandwidth utilization of DDR3 SDRAM.It has strong portability and provides a reference for the further research of multi⁃channel video data collaborative processing.