一种28Gbps高速SERDES发射器

A 28Gbps high-speed SERDES transmitter

介绍了一种基于源串联终端(Source-Series Terminated)驱动结构的高速(28Gbps)SERDES发射器设计.详述了整个TX的架构与原理;采用数模混合控制的时钟占空比校准(DCC)电路,有效降低了DCD;并且改进了一种基于SST结构的阻抗调谐与加重均衡解耦的发射单元结构,大大降低了逻辑控制的复杂程度.该发射器电路可用于对传输速率要求在1 Gbps~28 Gbps的FPGA.设计采用了中芯国际14 nm FinFET工艺制作,样品测试结果显示,输出速率在28 Gbps速率下时,发射器指标满足PCIE 4.0协议标准.

A high-speed(28Gbps)interface transmitter design based on a Source-Series Terminated drive structure is introduced.The architecture and principle of the entire TX are described in detail;the clock duty cycle calibration(DCC)circuit with digital-analog hybrid control is used to effectively reduce the DCD;and a transmitter unit based on SST structure impedance tuning and weighted balance decoupling is improved The structure greatly reduces the complexity of logic control.The transmitter circuit can be used for FPGAs that require a transmission rate of 1 Gbps~28 Gbps.The design is made with SMIC14 nm FinFET technology.The sample test results show that when the output rate is 28 Gbps,the transmitter's indicators meet the PCIE 4.0 protocol standard.