延时信号消除锁相技术及其延时误差影响分析

Phase-locked Technique of Delay Signal Cancellation and Analysis of the Effect of Delay Error

基于延时信号消除(DSC)的锁相环(PLL)技术可以实现指定次谐波和负序分量的影响消除,快速捕获非理想电网电压正序分量的相位。然而受限于现场应用的采样速率,延时信号往往无法按预期精准实现,延时误差不可避免。而目前针对这种延时误差对DSC PLL的影响及在此基础上的参数选型约束未见报道。这里在描述DSC对正、负序分离及谐波消除机理的基础上,定量分析了延时误差的影响,并以此为依据,给出了基于给定精度约束的延时误差限值计算方法和采样频率选型原则,指导DSC锁相技术应用时的参数设计。最后通过实验验证了理论分析和参数设计方法的有效性与准确性。

The phase-locked loop(PLL) technique based on delay signal cancellation(DSC) can eliminate the influence of specified sub-harmonic and negative sequence components,and quickly capture the phase of positive voltage sequence components under non-ideal power grid.However,due to the limited sampling rate in field application,the delay signal can not be realized precisely as expected,and the delay error is inevitable.However,the effect of delay error based on DSC PLL and the constraints of parameter selection have not been reported.On the basis of describing the mechanism of DSC for positive and negative sequence separation and harmonic elimination,the influence of delay error is quantitatively analyzed,the calculation method of delay error limit based on given precision constraint and the selection principle of sampling frequency are given to guide the parameter design of DSC phase-locked technique.Finally,the validity and accuracy of the theoretical analysis and parameter design method are veri-fied by experiments.