一种低电压VCO-ADC的设计与校准方法

A low-voltage VCO-ADC design and calibration

提出了一种低电压压控振荡器(Voltage Controlled Oscillator,VCO)型模/数转换器(Analog-to-Digital Converter,ADC)的设计方法。设计采用180 nm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺,包含两个VCO-ADC子通道的分裂式ADC,每个通道均采用差分结构。利用伪随机方式分别为两个通道加入相差为180°的正、负扰动信号,使用查找表方法对带有扰动信号的数字输出进行校准,以提高VCO-ADC的精度。仿真结果表明,当电源电压为0.8 V、输入信号频率为834.96 Hz、采样速率为5 kS/s时,电路有效位数(Effective Number of Bits,ENOB)为11.38 bit,无杂散动态范围(Spurious Free Dynamic Range,SFDR)达到78.21 dB。工作电压较低,电路面积和功耗较小。

A low-voltage voltage controlled oscillator(VCO)analog-to-digital converter(ADC)design method is proposed.The design adopts 180 nm complementary metal oxide semiconductor(CMOS)process,a split ADC with two VCO-ADC sub-channels,and both channels adopt the differential structure.The pseudo-random method is used to add positive and negative disturbance signals with a phase difference of 180°to the two channels,and the digital output with the disturbance signal is calibrated by the look-up table method to improve the accuracy of the VCO-ADC.The simulation results show that when the power supply voltage is 0.8 V,the input signal frequency is 834.96 Hz,and the sampling rate is 5 kS/s,the effective number of bits(ENOB)of the circuit is 11.38 bits,and the spurious free dynamic range(SFDR)reaches 78.21 dB.The working voltage is low,the circuit area and power consumption are small.