基于片上肖特基二极管的高功率三倍频器设计

Design of high power tripler based on on-chip schottky diodes

提出了一种基于片上集成电容工艺和带阻滤波结构的高功率三倍频器设计方法。在倍频器输入端,首先对倍频器二极管的直流偏置馈电部分进行改进,在梁式引线结构基础上结合二氧化硅(SiO_(2))工艺实现了片上集成电容,同时解决了三倍频器的直流馈电和射频接地问题,实现电路功能集成的同时也提高了模型仿真精度。此外,在二极管的输入端采用带阻滤波器结构替代传统的低通滤波结构,在保证倍频器性能的同时进一步简化倍频器结构复杂度和尺寸。为进行验证,设计并加工测试了两款中心频率分别为110 GHz和220 GHz的双路功率合成三倍频器。实际测试结果表明,在输入功率500 mW条件下,110 GHz三倍频器的输出峰值功率达到了140 mW,峰值效率接近30%,带宽超过15 GHz;在输入功率300 mW条件下,220 GHz三倍频器的输出峰值功率达到了45 mW,峰值效率达到15%,带宽为15 GHz。两款倍频的测试结果均有优秀表现,验证了设计方法的有效性。

This paper presents a design method of high-power triple frequency multiplier based on on-chip integrated capacitor technology and band-stop filter structure.The DC bias circuits of the tripler was improved by using the on-chip integrated capacitor based on beam lead structure so that the DC feed and RF ground were achieved simultaneously.Also,a more compact structure of the tripler was built and the model accuracy was improved.Then,the bandstop filter was used to replace the traditional stepped impedance lowpass filter to suppress the third harmonic.Hence,the structure of the tripler is further simplified while the performance is improved.A 110 GHz tripler and a 220 GHz tripler were fabricated and measured,respectively.The results show that when the input power is 500 mW,the maximum output power of 110 GHz tripler reaches 140 mW with 30%peak efficiency.When the input power is 300 mW,the peak efficiency of 220 GHz tripler reaches 15%and the maximum output power is 45 mW.Performance of two triplers validates the design method.