基于双模互锁的抗三节点翻转锁存器设计

Design of Triple Node Upset Tolerant Latch Based on Dual Mode Interlock

随着半导体工艺的发展,集成电路对单粒子效应所引起的软错误更加敏感。为了减弱或消除软错误对集成电路的影响,提出了一种基于32 nm CMOS工艺的抗三节点翻转(TNU)锁存器。该锁存器通过两个互锁的单节点翻转自恢复单元与C单元相连来抗TNU。此外,由于使用时钟门控技术、快速传输路径以及较少的晶体管,使该锁存器的功耗和延迟较低。HSPICE仿真结果表明该锁存器能够抗TNU,与其他先进的辐射加固锁存器相比,该锁存器在减少晶体管数量约34%的情况下,其功耗和延迟分别降低了约58%和21%,而功耗延迟积降低了约68%,并且对工艺、电压和温度(PVT)的波动具有低灵敏度。

With the development of semiconductor technology, integrated circuits are more sensitive to soft errors caused by single event effects.To reduce or eliminate the influence of soft errors on inte-grated circuits, a triple node upset(TNU) tolerant latch based on 32 nm CMOS technology was proposed.The latch was connected to the C element through two interlocked single node upset self-recovery cells to tolerate TNU.Furthermore, due to the use of clock gating technology, high speed transmission path and fewer transistors, the power consumption and delay of the latch were lower.HSPICE simulation results show that the latch can tolerate TNU.Compared with other advanced radiation hardening latches, with a reduction in the number of transistors by about 34%,the proposed latch can achieve a reduction in power consumption and delay by about 58% and 21%,respectively, a reduction in power delay pro-duct by about 68%,and has low sensitivity to process, voltage and temperature(PVT) variations.