电力高端控制芯片封装协同设计、仿真与验证

Collaborative Design,Simulation and Verification for Power High-End Control Chip Package

芯片封装作为芯片协同设计的核心,与芯片设计端协同设计芯片布局和管脚分布,与印制电路板(PCB)设计端协同设计球栅阵列(BGA)焊球布局,并完成封装设计、优化与验证。时序仿真以I/O数据传输速率最高的双倍数据速率(DDR)同步动态随机存储器(SDRAM)模块为例,对整个链路进行仿真分析,在数据传输速率为1 333 Mibit/s、最差码型的情况下,仿真得到的数据信号DQ0眼图的眼宽为599.41 ps。电力控制芯片的电热仿真协同进行,芯片实际功耗为1.5 W、自然环境温度为32℃时,得到封装叠层的最大电流密度为104.28 A/mm^(2),各个电源在芯片焊盘处的压降均在2%之内,芯片的塑封表面中心仿真温度为52.9℃。在同样条件下测试,测得塑封表面中心温度为51.5℃,与仿真结果相比误差较小。

As the core of chip collaborative design, chip packaging collaborates with the chip design end to design chip layout and pins distribution, and with the printed circuit board(PCB) design end to design the solder ball layout of ball gate array(BGA),and completes the package design, optimization and verification.The timing simulation took the double data rate(DDR) synchronous dynamic random access memory(SDRAM) module with the highest I/O data transmission rate as an example to simulate and analyze the whole link.Under the condition that the data transmission rate is 1 333 Mibit/s and the worst code type, the aperture width of the simulated data signal DQ0 eye diagram is 599.41 ps.The electrothermal simulation of the power control chip was carried out in collaboration.When the actual power of the chip is 1.5 W and the natural environment temperature is 32 ℃,the maximum current density of package lamination is 104.28 A/mm^(2),the voltage drop of each power supply at the chip pad is within 2%,and the simulation temperature of the molding surface center of the chip is 52.9 ℃.Under the same conditions, the measured temperature of the molding surface center is 51.5 ℃,which has a smaller error compared with the simulation result.