新型PD协议芯片BMC解码电路的设计与验证

Design and verification of BMC decoding circuit for new PD protocol chip

提出了一种新型PD协议芯片BMC解码电路。在传统BMC解码电路的基础上,首先,将计数器从解码模块中分离出来并在解码模块内新增状态机,通过改变状态机的跳转条件实现了对单比特周期突变25%的BMC信号的解码;然后,新增的FIR滤波器使得Threshold值随Cnt值线性变化,实现了对周期多次连续变化的BMC信号成功解码;最后,利用Synopsys公司的Verilog Compiled Simulator进行仿真验证,证明了新方案可以对周期相差25%的相邻两位BMC信号解码,可以对周期以6.25%增加的连续十位进行解码。

This paper presents a new type of biphase mark coding(BMC)decoding circuit for PD protocol chip.Based on the traditional BMC decoding circuit,firstly,the counter is separated from the decoding module,and a state machine is added in the decoding module.By changing the jump condition of the state machine,the BMC signal with single bit period mutation of 25%is decoded.Then,a finite impulse response(FIR)filter is added to make the threshold value change linearly with the value of Cnt,so that the BMC signal with multiple continuous cycles can be decoded.Finally,the Verilog Compiled Simulator of Synopsys company is used for simulation verification,which proves that the new scheme can decode two adjacent BMC signals with a period difference of 25%,and decode ten consecutive BMC signals with a period increase of 6.25%.