基于多相滤波的四路并行抽样算法及实现

The four parallel sampling algorithm based on polyphase filtering and its implementation

在某型数字信号处理模块的研制中,需要使用高速A/D对射频信号进行采样,但由于系统时钟生成模块无法输出320 MHz时钟,从而导致该高速A/D无法在320 MS/s采样率下工作。为解决该问题,首先设置A/D采样率为960 MS/s,然后在FPGA中对采样信号进行3倍采样后得到320 MS/s的采样输出。该高速A/D与FPGA采用标准的JESD204B接口,所以在FPGA中利用JESD204B IP核对高速信号进行了1:4串并转换,再对串并转换信号进行多相滤波、抽取降样处理后输出。首先介绍了课题的背景,然后对信号处理模块的组成、功能和性能指标进行了简要的说明,对系统在320 MS/s采样率下存在的问题进行了深入分析,针对该问题提出了四路并行抽样算法。并基于该算法,利用MATLAB进行了系统建模并进行仿真,仿真结果与预期一致。选取Xilinx公司的高性能FPGA,并结合系统模型中的低通滤波器参数对电路进行实现,最后搭建数字信号处理模块与Vivado等软件工具的软硬件联合测试环境进行验证并给出实验结果。

In the development of a certain type of digital signal processing module,high-speed AD samples the RF signal,but the clock generation module cannot output the 320 MHz clock,which causes the high-speed AD to work normally at the sampling rate of 320 MS/s.Therefore,in a high-performance FPGA,the signal is first sampled 3 times,and the JESD204B IP core performs a 1:4 serial-to-parallel conversion on the high-speed signal.Finally,the serial-to-parallel conversion signal is subjected to polyphase filtering and down sampling.The article first introduces the background of the subject,then briefly describes the composition,function and performance indicators of the signal processing module,and deeply analyzes the problems existing in the sampling rate of 320 MS/s,and proposes four parallel sampling algorithm for the problem.Based on the algorithm,the system was modeled and simulated by MATLAB,and the simulation results were consistent with expectations.It selects Xilinx′s high-performance FPGA and combines the low-pass filter parameters in the system model to implement the circuit.Finally,the digital signal processing module and the software and hardware joint test environment of software tools such as Vivado are built to verify and give the experimental results.