一款集成VCO宽带频率合成器

An Integrated VCO Wideband Frequency Synthesizer

采用0.35μm SiGe BiCMOS工艺设计了一款集成压控振荡器(VCO)宽带频率合成器。该锁相环(PLL)型频率合成器主要包括集成VCO、鉴频鉴相器、可编程电荷泵、小数分频器等模块。其中集成VCO采用3个独立的宽带VCO完成对频率的覆盖;鉴频鉴相器采用动态逻辑结构;小数分频器中Σ-Δ调制器模数可编程,可以精确调制多种分频值。测试结果表明,在电源电压3.3 V、工作温度-40~85℃的条件下,该芯片输出频率为137.5~4400 MHz,频偏100 kHz处的相位噪声为-104 dBc/Hz,频偏1 MHz处的相位噪声为-131 dBc/Hz,归一化本底噪声为-215 dBc/Hz。芯片面积为3.8 mm×4 mm。该频率合成器能为通信系统提供低相位噪声或低抖动的时钟信号,具有广阔的应用前景。

An integrated voltage-controlled oscillator(VCO)wideband frequency synthesizer was designed using 0.35μm SiGe BiCMOS process.The phase-locked loop(PLL)frequency synthesizer mainly included an integrated VCO,a phase frequency detector,a programmable charge pump,and a fractional frequency divider.In detail,the integrated VCO was composed of three independent wideband VCOs to complete the frequency coverage;the dynamic logic structure was adopted by the phase frequency detector;the modulus of theΣ-Δmodulator could be programmed to accurately modulate a variety of frequency division values.The test results show that under the conditions of a power supply voltage of 3.3 V and an operating temperature of-40℃to+85℃,the output frequency range of the chip is 137.5-4400 MHz,the phase noise is-104 dBc/Hz@100 kHz and-131 dBc/Hz@1 MHz.The normalized noise floor is-215 dBc/Hz.The chip area is 3.8 mm×4 mm.The frequency synthesizer can provide low phase noise or low jitter clock signal for communication systems,which has a broad application prospect.