衬底去边宽度对高阻厚层硅外延片参数的影响

Influence of Substrate Edge Exclustion Width on Parameters of Thick Silicon Epitaxial Wafer with High Resistance

硅外延片的参数受衬底以及外延层两方面影响,研究了衬底背面SiO_(2)层边缘去除宽度(简称去边宽度)对高阻厚层硅外延片参数的影响。对比0、0.3和0.5 mm三种去边宽度硅外延片的参数发现,去边宽度对外延层厚度不均匀性没有影响,对外延层电阻率不均匀性影响巨大,外延层电阻率不均匀性与衬底去边宽度呈正比。衬底去边宽度也会影响外延片的外观、表面颗粒以及滑移线。进一步研究了去边宽度对后续制备MOS管在晶圆片内击穿电压分布的影响,发现去边宽度越宽,晶圆片内MOS管击穿电压差越大。综合考虑外延片及其制备器件参数,选择0.3 mm为制备高阻厚层硅外延片的最佳去边宽度,可以获得优良的外延片参数及器件特性。

The parameters of silicon epitaxial wafers are affected by both the substrate and the epitaxial layer.The influence of removal width of SiO_(2) layer edge on the backside of substrate(referred to as edge exclustion width)on the parameters of thick silicon epitaxial wafers with high resistance was studied.By comparing parameters of silicon epitaxial wafers with three edge exclustion widths of 0,0.3 and 0.5 mm,it is found that the edge exclustion width has no effect on the non-uniformity of the epitaxial layer thinkness,and a huge impact on the non-uniformity of the epitaxial layer resistivity.The non-uniformity of the epitaxial layer resistivity is directly proportional to the edge exclustion width of the substrate.Meanwhile,the edge exclustion width of substrate also affect the appearance,surface particles and slip of the epitaxial wafers.The influence of the edge exclustion width on the breakdown voltage distribution of MOSFETs subsequently prepared on wafers was further studied.It is found that the wider the edge exclustion width,the greater the breakdown voltage difference of MOSFETs across the wafer.Considering the parameters of the epitaxial wafer and prepared device comprehensively,the substrate edge exclustion width of 0.3 mm is the best choice for preparing the thick silicon epitaxial wafer with high resistance,thus the excellent epitaxial wafer parameters and the device characteristics can be obtained.