一种25Gbit/s CMOS自适应判决反馈均衡器

A 25Gbit/s CMOS Adaptive Decision Feedback Equalizer

基于65nm CMOS工艺,设计了一种25Gbit/s带有一个无限冲激响应抽头的自适应判决反馈均衡器。该均衡器中关键路径采用堆叠式选择器和锁存器组成的半速率预测式结构,以减小环路反馈延时。自适应模块采用改进的最小均方算法,以改善抽头系数的收敛性。输出缓冲采用改进的f_(T)倍增结构,以提升带宽并具有预加重功能。仿真结果表明,当信号速率为25Gbit/s时,该均衡器能够自适应地实现最高20dB衰减量的补偿,输出抖动小于10ps。1.2V电源供电时,整体电路在不同工艺角下的平均功耗约为120.5mW。

A 25Gbit/s adaptive decision feedback equalizer(DFE)with one infinite impulse response(IIR)tap was designed in a 65nm CMOS technology.In this DFE,a half rate speculative structure consisting of one stacked selector and two latches was adopted to reduce the feedback delay on the critical path.An adaptive engine based on the improved least mean square(LMS)algorithm was employed to improve the convergence of the tap coefficient.An improved f_(T) doubler was used as the output buffer for higher bandwidth and pre-emphasis.The simulation results showed that the DFE could adaptively compensate up to 20dB channel attenuation at 25Gbit/s signal rate while its output jitter was less than 10ps.The average power consumption of the whole circuit was about 120.5mW at differential process corners from a voltage supply of 1.2V.