单光子探测InGaAs雪崩焦平面像素级高分辨率低误码时间数字转换电路

Pixel-level high resolution and low error rate time-to-digital converter circuit of single photon detection InGaAs avalanche focal plane array

单光子探测在量子信息、生物医学、激光雷达成像等领域具有重要应用前景,InGaAs盖革雪崩焦平面具有单光子探测灵敏度,通过计量光子飞行时间实现距离探测,时间数字转换精度决定整个探测系统的测距精度,是近年来单光子探测领域的研究热点。设计了一款64×64面阵型像素级高分辨低误码时间数字转换阵列电路(Time to Digital Converter,TDC),采用局部共享型高中低三段式异步周期TDC结构。低段位TDC全阵列共享,基于压控延迟链(Voltage Control Delay Line,VCDL)分相时钟实现亚纳秒计时;中高段位每个像素独享,中段位采用分频计数器降低时钟频率,降低阵列整体功耗,高段位采用线性反馈移位寄存器实扩展计时量程并实现计时、数据存储、输出一体化。采用延迟采样方案显著降低了因段间计数时钟不匹配导致的数据锁存误码问题。采用0.18μm CMOS工艺流片,实测250 MHz参考时钟频率下分辨率0.5 ns,积分非线性-0.4~0.6 LSB,微分非线性-0.4~0.4 LSB,TDC转换单调,有效量程位数13位,20 kHz帧频功耗380.5 mW。

Single-photon detection has important application prospects in quantum information,biomedicine and laser radar 3 D imaging.InGaAs Geiger avalanche focal plane has single-photon sensitivity.Distance detection is achieved by measuring time of photon flight.Time-to-digital conversion accuracy determines the ranging accuracy of the detection system and this direction is the focus of single photon detection in recent years.A high resolution and low error rate 64×64 array type pixel level time-to-digital converter(TDC)circuit adopting threestage asynchronous periodic counter structure was designed for InGaAs Geiger-mode avalanche focal plane array applications.Sub-nanosecond time resolution was realized by a voltage-controlled delay chain as well as a fine TDC that was shared by the entire array.The pixel level middle and coarse TDC used a divider counter to reduce the clock frequency and a linear feedback shift register to achieve a large time range,respectively.The highsegment coarse TDC can achieve timing,data storage and output integration through the register chain.The data conversion error rate originating from the mismatch of counting clocks between different stages was significantly reduced by incorporating of a delayed sampling scheme.A timing resolution of 0.5 ns at a reference clock frequency of 250 MHz,an integral nonlinearity of-0.4 to 0.6 LSB,a differential nonlinearity of-0.4 to 0.4 LSB,an effective digit of 13 bits,and a power consumption of 380.5 mW at 20 kHz frame rate are attained based on a0.18μm digital-analog hybrid CMOS technology.The TDC remains monotonous within the conversion range.