期刊文献+

基于0.35μm CMOS工艺的高温高压LDO芯片设计 被引量:3

Design of high temperature and high voltage LDO using 0.35μm CMOS process
下载PDF
导出
摘要 基于X-FAB xa 0.35μm CMOS工艺,首先采用Cascode电流镜和高压管,设计了一种具有高电源抑制比且无需额外提供偏置模块的高温高压基准电路,在输入电压为5.5 V~30 V、工作温度为-55℃~175℃时,可获得稳定的0.9 V基准电压。接着针对负反馈环路的稳定性问题,根据动态零点补偿原理设计了一种新的动态零点补偿电路,使系统在全负载变化范围内保持稳定。同时配合其他过温保护、过压保护、过流保护和逻辑控制等电路模块,完成一款面积为2.8223 mm^(2)的高温高压低压差线性稳压器(LDO)芯片的设计。 In this paper, based on X-FAB xa 0. 35 μm CMOS process, a cascode current mirror and high voltage MOS transistors are used to design a high temperature and high voltage reference circuit with high power supply rejection ratio without additional bias circuit module, and thus, a stable 0. 9 V reference voltage can be obtained when the input voltage is in the range of 5. 5 V~30 V and the operating temperature is in the range of -55 ℃~175 ℃. Then, according to the principle of dynamic zero compensation, a new dynamic zero compensation circuit is designed to make the system to maintain stability in the full load voltage range. At the same time, with the design of other circuit modules such as over-temperature protection, over-voltage protection, over-current pro-tection and logic control circuit modules, a low-dropout linear regulator( LDO) chip with high temperature and high voltage is finally designed, the area of which is 2. 822 3 mm;.
作者 吴霞 鲍言锋 邓婉玲 黄君凯 Wu Xia;Bao Yanfeng;Deng Wanling;Huang Junkai(College of Information Science and Technology,Jinan University,Guangzhou 510632,China)
出处 《电子技术应用》 2021年第12期120-125,共6页 Application of Electronic Technique
基金 广东省自然科学基金(2020A1515010567)。
关键词 LDO CMOS 高温高压 0.35μm工艺 LDO CMOS high temperature and voltage 0.35μm process
  • 相关文献

参考文献3

二级参考文献13

  • 1竺士炀,林成鲁,高剑侠,李金华.WSi_2栅和Si栅CMOS/BESOI的高温特性分析[J].固体电子学研究与进展,1996,16(4):348-351. 被引量:1
  • 2考林基JP 武国英等(译).SOI的技术--21世纪的硅集成电路技术[M].北京:科学出版社,1993.169-170.
  • 3竺士炀 林成鲁 等.-[J].固体电子学研究与进展,1996,16(4):348-351.
  • 4武国英(译),SOI技术——21世纪的硅集成电路技术,1993年,169页
  • 5LEUNG K N,MOK P K T. A capacitor-free CMOS low dropout regulator with damping factor control frequency compensation [J]. IEEE J Sol Sta Circ,2003,38(11):1691-1702.
  • 6CHEN C Z,WING H K. Output Capacitor Free Adaptively Biased Low-Dropout Regulator for System on Chips[J]. IEEE Trans Elec Dev,may 2010,57(10):1017-1028.
  • 7Or P Y,Leung K N. An output-capacitor less low-dropout regulator with direct voltage-spike detection[J]. IEEE J Sol Sta Cite ,2010,45 (8):458-466.
  • 8HUANG W J, LIU S I. Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1- bit programmable capacitor array [J]. IET Circuits Devices Syst, 2008,3 ( 10):306-316.
  • 9ADI公司.ADPTl42手册[EB/OL].(2014-9)[2015-08-03].www.analog.com.
  • 10美信半导体器件公司.MMAXl5006$册[EB/OL].(2015).[2015-08-03].www.maximintegated.com.

共引文献4

同被引文献22

引证文献3

二级引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部