一种延时自校准数字时间转换器电路设计

A time delay self-calibration digital to time converter circuit design

为了校准由于工艺波动导致的数字时间转换器输出延时变化,提出了一种新型的自校准数字时间转换电路。电路由放大器、钟控比较器、数字时间转换器、时间电压转换电路及逻辑控制电路构成。校准电路在数字时间转换器每级延时单元增加电容阵列进行最大延时校准,通过时间电压转换电路将信号最大输出延时转换为电压,再将转换电压与校准电压的差值进行放大,放大后的结果经过比较器进行比较,比较结果通过控制电路调整延时单元负载电容大小,从而精确调整数字时间转换器的最大延迟,实现了数字时间转换器最大输出延时的自适应校准。数字时间转换器基于40 nm CMOS工艺设计,电源电压为1 V,输入时钟最高为200 MHz,在校准电压为650~860 mV范围内,实现了0.578~1.466 ns的数字时间转换器的最大输出延时校准,校准误差不超过1.25%。

In order to calibrate the digital to time converter output delay variation due to process fluctuation, a new self-calibrating digital to time conversion circuit is proposed. The circuit consists of amplifier, clock-controlled comparator, digital to time converter, time voltage conversion circuit and logic control circuit, the calibration circuit increases the capacitor array at each stage of the digital to time converter delay unit for maximum delay calibration, converts the signal maximum output delay time to voltage through the time voltage conversion circuit, and then converts the difference between the converted voltage and the calibrated voltage is amplified, and the amplified result is compared by a comparator, and the comparison result is used to adjust the load capacitance size of the delay unit through the control circuit, so as to precisely adjust the maximum delay of the digital to time converter and realize the adaptive calibration of the maximum output delay time of the digital to time converter. The calibration of the digital to time converter is based on a 40 nm CMOS process. The digital to time converter is designed based on a 40 nm CMOS process with a supply voltage of 1 V and an input clock of up to 200 MHz. In the calibration voltage range of 650-860 mV, the maximum output delay calibration of the digital to time converter is achieved in the range of 0.578-1.466 ns with a calibration error of no more than 1.25%.