期刊文献+

基于NRS1800的SRIO互连技术的研究与设计

Research and Design of SRIO Interconnection Technology Based on NRS1800
下载PDF
导出
摘要 现代信号处理系统中,处理器的性能不断提高,而同时期处理器的总线频率增长却相对缓慢,导致了处理器数据处理需求与总线所能提供数据能力的矛盾,并成为了制约系统性能的关键因素之一[1]。SRIO协议因为其传输速度快,可靠性强、灵活度高的优点,被作为一种解决总线速率的方法,广泛应用在多个模块的互连中,用以实现高速通信。本文基于国产SRIO交换芯片NRS1800,研究了在FPGA和PowerPC之间以及PowerPC之间实现SRIO协议的方法,并通过NRS1800实现了多个模块间的高速通信。同时利用软件对SRIO数据传输性能进行了验证,为国产化的高速信号处理平台的设计提供了参考[2]。 In the modern signal processing system,the performance of the processor is constantly improving,but the bus frequency of the processor is relatively slow at the same time,which leads to the contradiction between the data processing requirements of the processor and the data capability provided by the bus,and becomes one of the key factors restricting the performance of the system.SRIO protocol is widely used in the interconnection of multiple modules to achieve high-speed communication because of its advantages of fast transmission speed,strong reliability and high flexibility.Based on the domestic SRIO switching chip nrs1800,this paper studies the implementation of SRIO protocol between FPGA and PowerPC and between PowerPC,and realizes the high-speed communication between multiple modules through nrs1800.At the same time,the data transmission performance of SRIO is verified by software,which provides a reference for the design of domestic high-speed signal processing platform.
作者 王浩宇 李雨航 李龙杰 张皓林 WANG Hao-Yu;LI Yu-Hang;LI Long-Jie;ZHANG Hao-Lin(China Ordnance Equipment Group Automation Institute Co.,Ltd.,Mianyang Sichuan 621000,China)
出处 《机电产品开发与创新》 2021年第6期28-30,共3页 Development & Innovation of Machinery & Electrical Products
关键词 信号处理系统 SRIO NRS1800 POWERPC FPGA Signal processing system SRIO NRS1800 PowerPC FPGA
  • 相关文献

参考文献5

二级参考文献21

  • 1高毅,刘永强,梁小虎.基于串行RapidIO协议的包交换模块的设计与实现[J].航空计算技术,2010,40(3):123-126. 被引量:6
  • 2尹亚明,李琼,郭御风,刘光明.新型高性能RapidIO互连技术研究[J].计算机工程与科学,2004,26(12):85-87. 被引量:20
  • 3Fuller S.RapidIO嵌入式系统互连[M].王勇,译.北京:电子工业出版社,2006-06.
  • 4RapidIO Trade Association. RapidlO Interconnect Spcification(Rev. 1.3)[Z]. 2005.
  • 5Hennessy J L, David A. Patterson Computer Architecture: A Quantitative Approach[M]. [S. l.]: Elsevier Science, 2003.
  • 6PCI Special Interest Group. PCI Local Bus Specification(Rev. 2.2)[Z]. 1998.
  • 7Jennie Ltd.. SRIOPCI Bridge Datasheet(V1.4)[Z]. 2006.
  • 8Sam Fuller等著,王勇,林粤伟,吴冰冰等译.RapidIO嵌入式系统互连[M].北京:电子工业出版社,2006.
  • 9RapidlO Specifications 1.3[Z]. www.rapidio.org/specs/current
  • 10LogiCORE RapidlO Logical I/O and Transport Layer v4.1.

共引文献26

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部