压接式IEGT寄生电感对其内部并联支路均流特性的影响研究

Study on Current Sharing of Parallel Branches Influenced by Parasitic Inductance Within PP-IEGT

压接式注入增强门极晶体管(press pack injection enhanced gate transistors,PP-IEGT)通过并联多个芯片增加其额定容量,然而芯片所在空间位置的差异会导致封装内寄生电感的分布不均,引发并联芯片间的电流分布不一致及热分布不均和芯片热失效。为准确分析PP-IEGT封装内寄生电感对并联芯片电流均衡性的影响,文中首先利用串联谐振曲线,提取单芯片子模组、凸台和驱动回路等组件的寄生电感,利用S参数法对测量的电感值进行验证。搭建双脉冲测试平台,结合实验数据和有限元仿真,研究寄生电感对并联芯片电流均衡性和电磁特性的影响。结果表明,寄生电感是影响电流分布的重要因素,驱动回路的寄生参数与距离栅极信号入口的长度成正比。随着PP-IEGT额定容量的增大,并联支路数量的增多,芯片间电参数不均问题更加严重;改变凸台的栅极豁角结构有助于提高电磁参数分布的均衡性。

Press pack injection enhanced gate transistors(PP-IEGTs) parallel multi-chip within the packaging to increase the rating power. However, chips at different locations introduce different parasitic inductors, which leads to inconsistent current distribution between parallel chips, and further causes uneven thermal distribution and chip thermal failure. In order to accurately analyze the effect of parasitic inductors on current sharing among parallel chips, this study extracted the parasitic inductances of single chip module, drive circuit and pillars of the PP-IEGT by using the series resonance, and the inductances were verified based on the S parameter method. The current sharing and electromagnetic characteristics among chips were studied based on the platform of double pulse test. The results show that the parasitic inductance is an important factor to affect the current sharing.The parasitic parameters of the drive circuit are proportional to the length of the gate signal inlet. With the rated power and parallel branches increase, the uneven electrical parameters among chips become more serious. It is helpful to improve the evenness of electromagnetic parameters distribution by changing the gate angle structure of the pillars.