一种面积优化的高精度音频∑-△DAC数字前端实现

Implementation of an area optimized low power audio∑-△DAC digital

为实现高精度音频2-ODAC数字前端的微面积目标,本论文提出了一种数字前端电路面积优化的新方法.首先,优化了有限冲击响应(FIR)滤波器的系统结构。减小了硬件开销;然后提出了一种RADIX-2'算法以利用滤波器系数之间共享基本式,从结构到系数的优化,减小了滤波器的面积,最后,优化了的3阶4bit的∑-△调制器结构替代单比特量化器,克服了随机抖动的问题和降低了模拟重建滤波器的实现;同时分析调制器的信噪比与系数精度的关系,并采取折中的方法通过移位来实现精简后的系数,以最小的精度代价实现Z-0调制器的面积优化.通过FPGA平台验证了其功能,在1.2 V的工作电压下,其功耗为42μW,信噪比和动态范围分别是122 dB和120 dB,在TSMC 90 nm CMOS的工艺下,其芯片面积为0.051 mm^(2).结果表明,实现了高性能、低面积的要求.

In order to achieve the micro area target of high-precision audio sigma delta DAC digital front-end,a new method of area optimization of digital front-end circuit is proposed in this paper.Firstly,the system structure of FIR filter is optimized to reduce the hardware cost;secondly,a radix-2r algorithm is proposed to reduce the filter area by using the shared basic formula among the filter coefficients from structure to coefficient optimization;finally,the optimized 3-order 4-bit sigma delta modulator structure replaces the single bit quantizer to overcome the problem of random jitter and noise At the same time,the relationship between the signal-to-noise ratio of the modulator and the accuracy of the coefficients is analyzed,and a compromise method is adopted to realize the reduced coefficients by shifting,so as to realize the area optimization of the sigma delta modulator with the minimum cost of accuracy.The power consumption is 42μW,SNR and dynamic range are 122 dB and 120 dB respectively at 1.2 V.The chip area is 0.051 mm^(2)in TSMC 90 nm CMOS process.The results show that the requirement of high performance and low area is realized.