基于以太网通信的高采样率ADC交织校准实现

Interleaved calibration of high sampling ADC based on Ethernet communication

提出了一种针对高采样率时间交织模数转换器(TIADC)存在的失调失配误差(Offset)、增益失配误差(Gain)、时间失配误差(Skew)的片外交织校准实现方案,基于统计近似的时间交织校准算法,通过以太网通信将待校准通道量化信息传入PC机进而提取失配参数,负反馈的形式对误差进行补偿。该方案不受高速数据传输解扰与同步的影响,在误差提取阶段不消耗逻辑资源,支持各类大规模、大消耗校准算法,开发周期短。应用于自主研发的3GS/s-12bit四路交织TIADC中,在存在其他非理想因素情况下,在2.5G输入信号带宽内,测试结果显示采用交织校准算法技术后,ADC有效位数(ENOB)平均提高了2.69bits,校准后的无杂动态范围(SFDR)平均提高了29.73dBc,证明该算法及校准方案的有效性。

This paper presents an off-chip interleave calibration scheme for the Offset error,Gain error and Skew error of the high sampling rate time-interleaved analog-to-digital converter(TIADC).A time-interleave calibration algorithm is based on statistical approximation.Through Ethernet communication,the quantization information of the channel to be calibrated is transmitted to the PC to extract the mismatch parameters,and the error is compensated in the form of negative feedback.The scheme is not affected by high speed data transmission and synchronization,does not consume logical resources in error extraction stage,supports various large-scale and high-consumption calibration algorithms,and has a short development cycle.When applied to the self-developed 3GS/s-12bit four-way interleaving TIADC,the test results show that the ADC effective bit(ENOB)is increased by 2.69bits on average in the 2.5Ginput signal bandwidth under the condition of other non-ideal factors.The calibrated SFDR improved by an average of 29.73dBc.It is proved that the algorithm and the calibration scheme are effective.