基于概率计算的TPC译码算法研究与FPGA设计

Research on TPC decoding algorithm based on probability calculation and FPGA design

目前TPC码(Turbo乘积码)常用的译码算法为Pyndiah-Chase-II算法,但Pyndiah-Chase-II算法在搜索最不可靠输入比特位置和最短欧氏距离码字的过程中,涉及大量的排序运算、复杂的分支结构和存储调度使其非常不利于集成电路硬件实现。针对上述问题,提出一种基于概率计算的TPC译码算法,该算法包括信息输入层、随机比特流生成层、BCH硬判决层、BCH&CRC校验层、输出层,其TPC码的子码采用BCH码,通过MATLAB软件进行译码算法的程序设计并完成译码性能和译码延时的仿真。仿真结果表明,该译码算法能够达到和传统的Pyndiah-Chase-II算法相同的译码性能,平均只需要两次迭代即可实现正确译码,能有效地降低译码的延时。最后完成基于FPGA的硬件设计,BCH硬判决层采用查找表方式实现,其他层的逻辑结构简单,均为门级操作,所以能够大幅度减小硬件开销和降低功耗,易于用集成电路实现。

The common decoding algorithm for TPC codes(Turbo product code)is the Pyndiah-Chase-II algorithm,but the Pyndiah-Chase-II algorithm involves a large number of sorting operations,complex branching structures and storage scheduling in the process of searching for the least reliable input bit positions and shortest Euclidean distance code words making it very unfavorable for integrated circuit hardware implementation.In order to solve these problems,proposing a TPC decoding algorithm based on probabilistic computation,the algorithm includes information input layer,random bit stream generation layer,BCH hard judgment layer,BCH&CRC check layer,and output layer,and the sub-code of TPC code adopts BCH code,program design of decoding algorithm and simulation of decoding performance and decoding delay by MATLAB software.The simulation results show that the decoding algorithm can achieve the same decoding performance as the traditional Pyndiah-Chase-II algorithm,and it only needs two iterations on average to achieve correct decoding,which can effectively reduce the decoding delay.Finally,the FPGA-based hardware design is completed.The BCH hard judgment layer is implemented by the lookup table method,and the logic structure of other layers is simple and all are gate-level operations,so it can significantly reduce the hardware overhead and power consumption,and is easy to implement with integrated circuits.