基于通道自适应动态网络剪枝算法的FPGA加速器设计与实现

Design of FPGA Accelerator Based on Dynamic Network Pruning Algorithm

深度神经网络在移动端的部署是其在实际应用中很重要的环节,但是网络的规模越来越庞大,为了减少网络模型推理时的计算成本,提出一种动态神经网络剪枝算法。通过改进激活函数,依据输入选择不同的网络通道,在推理过程中动态选择要运算的网络结构。为了使该算法在实际使用中加速明显,采用现场可编程门阵列(Field Programmable Gate Array,FPGA)设计了一款适应动态剪枝算法的硬件加速器,专门针对动态通道自适应选择。实验在ZYNQ开发板上进行,根据开发板的硬件资源情况设计卷积运算和动态选择的运算单元,采用ResNet网络簇在CIFAR-10和CIFAR-100数据集验证加速器的效果,同时与GPU运算的精度、速度进行对比。

The deployment of deep neural networks on the mobile terminal is a very important part of its practical Application,but the scale of the network is getting larger and larger.In order to reduce the computational cost of network model inference,a dynamic neural network pruning algorithm is proposed.By improving the activation function,different network channels are selected according to the input,and the network structure to be calculated is dynamically selected during the inference process.In order to make the algorithm accelerate significantly in actual use,a hardware accelerator that adapts to the dynamic pruning algorithm is designed by using a field programmable gate array FPGA,specifically for dynamic channel adaptive selection.The experiment is carried out on the ZYNQ development board.The convolution operation and dynamically selected operation unit are designed according to the hardware resources of the development board.The ResNet network cluster is used to verify the effect of the accelerator on the CIFAR-10 and CIFAR-100 data sets.Compare accuracy and speed.