低噪声高分辨IC测试系统设计

The Design of Low Noise and High Resolution Acquisition Circuit of IC Test System

集成电路(IC)测试要求高速、高分辨率、高信噪比的信号采集系统,设计一套合适的采集系统具有极其重要的意义。论文分析了IC测试系统的组成原理,设计了低噪声信号调理电路并分析噪声系数;设计了可调相位延迟的时钟采样电路,有效实现低抖动的延迟;分析了误差对系统的影响,建立时间交替采样模型,有效校正了误差。测试表明,系统可有效实现高速高分辨的IC采集系统,达到16位分辨率、1 G采样率,波形误差达到63 dB,有效位数达到近12位,达到设计的要求。

The integrated circuit(IC)tester requires a high-speed,high-resolution,and high-signal-to-noise ratio signal acquisition system.It is of great significance to design a suitable acquisition system.The composition principle of the IC test system is analyzed,a low-noise signal conditioning circuit and the noise figure is analyzed;a clock sampling circuit with adjustable phase is designed to delay effectively low jitter;analyzes the impact of errors on the system,and the time The alternate sampling model is set,the error is effectively adjusted.Tests show that the system can effectively implement a high-speed and high-resolution IC acquisition system,with a resolution of 16 bits,a sampling rate of 1 G,a waveform error of 63 dB,and an effective number attain to nearly 12 bits,which meets the design requirements.