适用于Sigma-Delta ADC的多抽取率数字滤波器设计

Design of multi-decimation rate digital filter for sigma-delta ADC

采用标准0.18μm工艺,设计了一种能改变抽取率并且适应不同信号带宽的应用于Sigma-Delta模数转换器的数字抽取滤波器。该滤波器采用多级抽取,由级联积分梳状滤波器、补偿滤波器和半带滤波器组成。实现的数字滤波器抽取率可以在64、128、256、512中变化,并且补偿滤波器和半带滤波器的带宽可调整。滤波器版图尺寸0.6 mm×0.6 mm。在1.98 V工作电压下,最大总功耗约为2 mW,最高信噪比达到110.5 dB。当补偿滤波器和半带滤波器的通带截止频率根据带宽选择从最高降到最低时,可分别节省56%和39%的功耗;当滤波器功耗降至最小69.63μW时,所能处理的带宽为390.6 Hz,信噪比为107.8 dB。

Based on the standard 0.18μm process,a digital decimation filter applied to the Sigma-Delta analog-to-digital converter is designed,which can change the decimation rate and adapt to different signal band widths.The filter adopts multi-stage decimation and consists of a cascaded integrator comb filter,a compensation filter and a half-band filter.The realized digital filter can be changed in the decimation rate of 64,128,256 and 512.Compensation filters and half-band filters of different bandwidths are also designed.The filter area is 0.6 mm×0.6 mm.Under 1.98 V working voltage,the total maximum power consumption is about 2 mW,and the highest signal-to-noise ratio reaches 110.5 dB.When the passband frequency of the compensation filter and the half-band filter is selected according to the bandwidth from the highest to the lowest,it can save 61%and 53%of the power consumption respectively;When the filter power consumption being the smallest 69.63μW,the bandwidth that can be processed is 390.6 Hz,and the signal-to-noise ratio is 107.8 dB.