一种LVTTL电平输出的恒比定时电路

A Constant Fraction Discrimination Circuit with LVTTL Level Output

介绍了一种LVTTL电平输出的恒比定时电路。该电路通过信号放大、比较、电平转换,最终接入FPGA芯片,在FPGA芯片内部用延迟链方式直接实现测时功能。电路采用LVTTL电平输出,FPGA端可以直接识别该电平,与传统的设计相比,该设计省去了专用测时芯片,节约了成本,兼顾了体积要求。同时,该电路有望解决激光雷达系统功耗大、定时精度不高的问题。

This paper introduces a constant fraction discrimination circuit with LVTTL level output.Through signal amplification,comparison and level conversion,the circuit is finally connected to FPGA chip,and the time measurement function is directly realized by delay chain in FPGA chip.The circuit adopts LVTTL level output,and the FPGA chip can directly identify the level.Compared with the traditional design,this design eliminates the special time measuring chip,saves the cost and takes into account the volume requirements.At the same time,the circuit is expected to solve the problems of high power consumption and low timing accuracy of lidar system.