一种低杂散的小数分频锁相环

A Fractional Phase-Locked Loop with Low Spurious

基于0.18μm CMOS工艺,设计了一种锁定频率范围在1.8~2.4 GHz的电荷泵锁相环。采用高性能的鉴频鉴相器、电荷泵以及三阶Σ-Δ调制器,减小了输出时钟的参考杂散。在Σ-Δ调制器中引入线性反馈移位寄存器(LFSR),生成伪随机序列,进一步降低了小数杂散。仿真结果表明,在0.3~1.5 V输出电压范围内,锁相环的电流失配比仅为0.1%,小数杂散为-50 dBc@1 MHz。

A charge pump phase-locked loop with a locking frequency range of 1.6~2.4 GHz was designed in a 0.18 μm CMOS process. A high performance frequency discriminator, a charge pump and a third-order Σ-Δ modulator were adopted to reduce the reference spurs on output clocks. By introducing LFSR into the Σ-Δ modulator, a pseudo-random sequence was generated and the fractional spurs was further reduced. The simulation results showed that the current mismatch ratio was only 0.1% and the fractional spur was-50 dBc @1 MHz at 0.3~1.5 V output voltage.